1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit technology. More specifically, it relates to an electrostatic discharge protection circuit which can record any electrostatic discharge event occurring during the phases of testing, installation, and use, etc.
2. Description of the Prior Art
Electrostatic discharge, ESD hereinafter, is a common phenomenon that occurs during the handling of semiconductor integrated circuit, IC hereinafter, devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stressing typically can occur during a testing phase of IC fabrication, during installation of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Therefore, an ESD protection circuit is required to prevent ESD damage to the internal circuit of an IC.
FIG. 1 schematically depicts a conventional ESD protection circuit. In the drawing, reference numeral 1 designates an IC pad, which is electrically connected to the internal circuit 2 of the IC device. The conventional ESD protection circuit essentially comprises an N-type metal-oxide-semiconductor field-effect transistor (MOSFET) 10, which is configured with its drain connected to the IC pad 1, and with its gate and source tied to circuit grounding node V.sub.SS. Accordingly, the breakdown of the NMOS device 10 provides a direct ESD discharge path from the pad 1 to V.sub.SS.
However, except in the case that permanent damage is caused to the internal circuit 2, the conventional ESD protection circuit can not record whether or not any ESD event occurs during the phases of testing, installation, or use, etc.